Deutsch   English   Français   Italiano  
<2667d4e23b45172d4d618fbc6fd4cee8@www.novabbs.org>

View for Bookmarking (what is this?)
Look up another Usenet article

Path: ...!weretis.net!feeder9.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail
From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Arguments for a sane ISA 6-years later
Date: Sun, 4 Aug 2024 19:38:44 +0000
Organization: Rocksolid Light
Message-ID: <2667d4e23b45172d4d618fbc6fd4cee8@www.novabbs.org>
References: <b5d4a172469485e9799de44f5f120c73@www.novabbs.org> <2024Jul26.190007@mips.complang.tuwien.ac.at> <v811ub$309dk$1@dont-email.me> <2024Jul29.145933@mips.complang.tuwien.ac.at> <v88gru$ij11$1@dont-email.me> <2024Jul30.114424@mips.complang.tuwien.ac.at> <v8bi3e$16ahe$1@dont-email.me> <2024Aug1.191028@mips.complang.tuwien.ac.at> <gLPqO.1578$vu%c.859@fx08.iad> <55b647d46e79c54dc1261bbd037db3ac@www.novabbs.org> <ojSqO.21621$a6n5.10286@fx15.iad> <12d7fbb12f475a46ebce3e22fa4920ad@www.novabbs.org> <FI5rO.3432$1w_2.3356@fx48.iad>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 8bit
Injection-Info: i2pn2.org;
	logging-data="1465722"; mail-complaints-to="usenet@i2pn2.org";
	posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A";
User-Agent: Rocksolid Light
X-Rslight-Site: $2y$10$oQvjdLYM7wT3rB3i8DyMx.Iz.XpVfxM8fZrwbM8sQigAz1EfZN40y
X-Spam-Checker-Version: SpamAssassin 4.0.0
X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8
Bytes: 3410
Lines: 54

On Fri, 2 Aug 2024 14:05:25 +0000, Scott Lurndal wrote:

> mitchalsup@aol.com (MitchAlsup1) writes:
>>On Thu, 1 Aug 2024 20:34:28 +0000, Scott Lurndal wrote:
>>
>>
>>>>> In addition, ARM64 CPUs include allocation hints in
>>>>> the memory type such as 'read allocate', 'transient read allocate',
>>>>> 'write allocate' as well has having optionally multiple coherency
>>>>> domains (inner and outer sharable).
>>>>
>>>>Sorry, I don't understand the word 'allocate' ?!?
>>>
>>> "allocate a cache line".
>>>
>>> Example would be a DMA request with the 'read allocate' hint
>>> is allowed to be allocated in LLC instead of being stored in
>>> DRAM.
>>>
>>> Used when software expects the DMA data to be immediately.
>>
>>Thanks for the explanation.
>>
>>In my case LLC is simply the front end for DRAM so a device
>>write will spew data into LLC where it will wait to be written.
>
> I'm not sure that's a good idea.    Large DMAs are common
> (e.g. reading pages of data in a single I/O) and the data
> from the DMA is not always used by the CPU.  Evicting LLC lines to
> accomodate a file copy, for example, seems less than optimal.

Fair enough. But after thinking abut this for a while, does the
process performing the file copy even know it is doing a file
copy ?? for example::

cat ../mydir/myfile > ../yourdir/yourfile

Which kind of applications know they are doing Input that will
not be used rather presently ??

It seems to me that a file copy application would understand
that writing of DRAM is irrelevant when the true destination
is another sector on another disk, and any means to connect
those does is more than sufficient.

>
>>When using memove() or memset() data is moved on page sized
>>boundaries over the "bus".
>
> IME the majority of memset calls are for relatively small
> (less than a page) regions.

Yes, but the interconnect is designed to move large chunks
atomically. And the size of that chunk is "within a page
boundary"