Path: ...!weretis.net!feeder9.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: Computer architects leaving Intel... Date: Wed, 18 Sep 2024 14:27:28 +0000 Organization: Rocksolid Light Message-ID: <77a593b0e8dcb7e4f38c006d3a148cdc@www.novabbs.org> References: <86r09ulqyp.fsf@linuxsc.com> <2024Sep8.173639@mips.complang.tuwien.ac.at> <2024Sep10.101932@mips.complang.tuwien.ac.at> <2024Sep11.123824@mips.complang.tuwien.ac.at> <867cbhgozo.fsf@linuxsc.com> <20240912142948.00002757@yahoo.com> <20240915001153.000029bf@yahoo.com> <20240915154038.0000016e@yahoo.com> <2024Sep15.194612@mips.complang.tuwien.ac.at> <45fb24ca46af5c388b0a44af2f72ddf6@www.novabbs.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="2533468"; mail-complaints-to="usenet@i2pn2.org"; posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A"; User-Agent: Rocksolid Light X-Spam-Checker-Version: SpamAssassin 4.0.0 X-Rslight-Site: $2y$10$9NuJSl0GeRJpk05XQH8In.9Ujn2uk3SBf/jKIqBjNr5hpGVI2VH4S X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8 Bytes: 3229 Lines: 51 On Wed, 18 Sep 2024 4:00:43 +0000, BGB wrote: > On 9/17/2024 6:04 PM, MitchAlsup1 wrote: >> Still limited to 32-bit displacement from IP. >> >> How would you perform the following call:: >> current IP = 0x0000000000001234 >> target  IP = 0x7FFFFFFF00001234 >> >> This is a single (2-word) instruction in my ISA, assuming GOT is >> 32-bit displaceable and 64-bit entries. >> > > Granted, but in plain RISC-V, there is no real better option. > > If one wants to generate 64-bit displacement, and doesn't want to load a > constant from memory: > LUI X6, Disp20Hi //20 bits > ADDI X6, X6, Disp12Hi //12 bits > AUIPC X7, Disp20Lo > ADD X7, Disp12Lo > SLLI X6, X6, 32 > ADD X7, X7, X6 How very much simpler is:: MEM Rd,[IP,Ri< > Which is sort of the whole reason I am considering hacking around it > with an alternate encoding scheme. Just put in real constants. > > New encoding scheme can in theory do: > LEA X7, PC, Disp64 > In a single 96-bit instruction. Where is the indexing register? > ------------ >> >> AUPIC is (and remains) a crutch (like LUI from MIPS) >> a) it consumes an instruction (space and time) >> b) it consumes a register unnecessarily >> c) it consumes power that direct delivery of the constant would not > > Yeah, pretty much. > LUI + AUIPC + JAL, eat nearly 27 bits of encoding space. >