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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Misc: BGBCC targeting RV64G, initial results...
Date: Fri, 18 Oct 2024 02:28:45 +0000
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On Thu, 17 Oct 2024 0:03:26 +0000, BGB wrote:

> On 10/16/2024 5:16 PM, MitchAlsup1 wrote:
>> On Wed, 16 Oct 2024 20:23:08 +0000, BGB wrote:
>>
>>>
>>> Ironically, one of the main arguable use-cases for old Fortran style IF
>>> statements is implementing the binary dispatch logic in a binary
>>> subdivided "switch()", but not enough to justify having a dedicated
>>> instruction for it.
>>>
>>> Say:
>>>    MOV  Imm, Rt  //pivot case
>>>    BLT  Rt, Rx, .lbl_lo
>>>    BGT  Rt, Rx, .lbl_hi
>>>    BRA  .lbl_case
>>
>> With a 64-bitinstruction one could do::
>>
>>      B3W   .lbl_lo,.lbl_zero,.lbl_hi
>>
>> rather straightforwardly.....
>
> Possibly, but the harder part would be to deal with decoding and feeding
> the instruction through the pipeline.

Feed the 3×15-bit displacements to the branch unit. When the condition
resolves, use one of the 2 selected displacements as the target address.

> Granted, I guess it could be decoded as if it were a normal 3RI op or
> similar, but then split up the immediate into multiple parts in EX1.

Why would you want do make it 3×11-bit displacements when you can
make it 3×16-bit displacements.

     +------+-----+-----+----------------+
     | Bc   |  3W |  Rt |   .lb_lo       |
     +------+-----+-----+----------------+
     |   .lb_zero       |  .lb_hi        |
     +------------------+----------------+