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From: Lawrence D'Oliveiro <ldo@nz.invalid>
Newsgroups: comp.arch
Subject: Decrement And Branch
Date: Tue, 13 Aug 2024 09:00:25 -0000 (UTC)
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I thought loop-control instructions had fallen out of favour in the RISC 
era. But reading some IBM POWER (and PowerPC) docs has reminded me that 
that family does have such instructions. I don’t think any other RISC 
architecture does, though. POWER even has a special register (CTR, the 
“counter” register) for use with loop instructions, though it could also 
(along with LR, the “link” register) be used for indirect branches. 
(Obviously you need at least two registers with this property.)

The original designers of POWER clearly thought there was a point to 
having such instructions; do you agree?

The most common form of these will decrement the counter register, and 
only branch back to the top of the loop if the counter has not reached 
zero; if it is now zero, then fall through. However, the good old VAX (in 
its usual kitchen-sink fashion) had a whole set of variations, including 
one that decremented down to -1 instead of zero. And the Motorola 68000 
family only had the decrement down to -1 version.

This seemed to mystify quite a few assembly-language programmers. I wonder 
why it wasn’t a more popular idea ...