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From: BGB <cr88192@gmail.com>
Newsgroups: comp.arch
Subject: Re: Tonights Tradeoff
Date: Thu, 12 Sep 2024 03:21:54 -0500
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On 9/12/2024 12:37 AM, Thomas Koenig wrote:
> MitchAlsup1 <mitchalsup@aol.com> schrieb:
>> On Tue, 10 Sep 2024 7:00:00 +0000, BGB wrote:
>>
>>> On 9/9/2024 10:59 PM, Robert Finch wrote:
>>>>
>>>> Still trying to grasp the virtual vector method. Been wondering if it
>>>> can be implemented using renamed registers.
>>>>
>>>
>>> I haven't really understood how it could be implemented.
>>> But, granted, my pipeline design is relatively simplistic, and my
>>> priority had usually been trying to make a "fast but cheap and simple"
>>> pipeline, rather than a "clever" pipeline.
>>
>> "Good, Fast, Cheap; choose any 2" Lee Higbe 1982.
> 
> Still beeter than "Good, Fast, Cheap: Chose one."

One can take note of all my corner-cutting...

I was mostly trying to prioritize fast and cheap, but sadly it is 
neither as fast nor as cheap as I would want.



Though, ironically, will put at least some of the cost blame on RISC-V, 
which doesn't go quite so hard on the corner cutting.

But, one can maybe argue that it is a bit much to try to push for a 
64-bit ISA that only natively has 32-bit integer multiply, ...

Though, this is not to say that other possible implementations couldn't 
try to do everything "properly".