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Date: Wed, 30 Nov 2022 04:55:48 -0800 (PST)
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Subject: BugsBoard: an FPGA design for the Digilent Cmod S7
From: Myron Plichota <myronplichota@gmail.com>
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The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.

e.g. apps/color_toy.py:

include('FPGAburn/appload.py') # must be on the first line

# play with LD0 color

  ja(fwd('init'))

lbl('app_msg'); ascii('\r\npress BTN0 to reset')

# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])

# commands

lbl('ir') # char -> # increment red
  drop(); lld(red); inc(); lst(red); ret()

lbl('dr') # char -> # decrement red
  drop(); lld(red); dec(); lst(red); ret()

lbl('ig') # char -> # increment green
  drop(); lld(green); inc(); lst(green); ret()

lbl('dg') # char -> # decrement green
  drop(); lld(green); dec(); lst(green); ret()

lbl('ib') # char -> # increment blue
  drop(); lld(blue); inc(); lst(blue); ret()

lbl('db') # char -> # decrement blue
  drop(); lld(blue); dec(); lst(blue); ret()

lbl('command') # -> # execute a recognized command
  lld(arx_rdy)
  _if()
    lld(uart); dup(); cp(tx) # -> char # echo
    dup(); lbxor(ord('R')); jz(ir)
    dup(); lbxor(ord('r')); jz(dr)
    dup(); lbxor(ord('G')); jz(ig)
    dup(); lbxor(ord('g')); jz(dg)
    dup(); lbxor(ord('B')); jz(ib)
    dup(); lbxor(ord('b')); jz(db)
    drop() # none of the above
  _then()
  ret()

lbl('init')
  lit(app_msg); cp(tx_ascii)
  _begin()
    cp(command)
    lld(red); lst(pwm1)
    lld(green); lst(pwm2)
    lld(blue); lst(pwm3)
  _again()

lbl('app_end') # must be on the last line

BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.

Cheers - Myron Plichota