Path: ...!weretis.net!feeder6.news.weretis.net!i2pn.org!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: Stealing a Great Idea from the 6600 Date: Fri, 19 Apr 2024 18:40:45 +0000 Organization: Rocksolid Light Message-ID: References: <71acfecad198c4e9a9b14ffab7fc1cb5@www.novabbs.org> <1s042jdli35gdo092v6uaupmrcmvo0i5vp@4ax.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="1701640"; mail-complaints-to="usenet@i2pn2.org"; posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A"; User-Agent: Rocksolid Light X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8 X-Rslight-Site: $2y$10$J/tKTQjQApK1twCX.huhoOodK6F1F51ivO.yjreeiIgje4Z5CT7FK X-Spam-Checker-Version: SpamAssassin 4.0.0 Bytes: 3060 Lines: 53 John Savard wrote: > On Thu, 18 Apr 2024 23:42:15 -0600, John Savard > wrote: >>Each core can just switch between compute duty with N threads, and I/O >>service duty with 4*N threads - or anywhere in between. > So I hope it is clear now I'm talking about SMT threads, not cores. > Threads are orthogonal to cores. That was already clear. > But I did make one oversimplification that could be confusing. > The full instruction set assumes banks of 32 registers, one each for > integer and floats, the reduced instruction set assumes banks of 8 > registers, one each for integer and floats. > So one thread of the full ISA can be replaced by four threads of the > reduced ISA, both use the same number of registes. So how does a 32-register thread "call" an 8 register thread ?? or vice versa ?? What ABI model does the compiler use ?? When an 8-register thread takes an exception, is it handled by a 8-reg thread or a 32-register thread ?? > That's all right for an in-order design. But in real life, computers > are out-of-order. So the *rename* registers would have to be split up. In K9 we unified the x86 register files into a single file to simplify HW maintenance of the OoO state. > Since the reduced ISA threads are four times greater in number, their > instructions have four times longer to finish executing before their > thread gets a chance to execute again. Now all that forwarding logic is wasting its gates of delay and area without adding any performance. Now all those instruction schedulers are sitting around doing nothing. > So presumably reduced ISA > threads will need less agressive OoO, and 1/4 the rename registers > might be adequate, but there's obviously no guarantee that this would > indeed be an ideal fit. LoL. > John Savard