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From: "Edward Rawde" <invalid@invalid.invalid>
Newsgroups: sci.electronics.design
Subject: Re: Predictive failures
Date: Tue, 16 Apr 2024 21:16:45 -0400
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"John Larkin" <jjSNIPlarkin@highNONOlandtechnology.com> wrote in message 
news:p47u1j1tg35ctb3tcta5qevsfnhgnpcrsg@4ax.com...
> On Tue, 16 Apr 2024 13:39:07 -0400, "Edward Rawde"
> <invalid@invalid.invalid> wrote:
>
>
>>> On 17/04/2024 1:22 am, John Larkin wrote:
>>>> On Tue, 16 Apr 2024 09:45:34 +0100, Martin Brown
>>>> <'''newspam'''@nonad.co.uk> wrote:
>>>>> On 15/04/2024 18:13, Don Y wrote:
>>>
>
>>Yes I've seen that a lot.
>>The power rails in the production product came up in a different order to
>>those in the development lab.
>>This caused all kinds of previously unseen behaviour including an 
>>expensive
>>flash a/d chip burning up.
>>
>>I'd have it in the test spec that any missing power rail does not cause
>>issues.
>>And any power rail can be turned on and off any time.
>>The equipment may not work properly with a missing power rail but it 
>>should
>>not be damaged.
>
>
> Some FPGAs require supply sequencing, as may as four.
>
> LM3880 is a dedicated powerup sequencer, most cool.
>
> https://www.dropbox.com/scl/fi/gwrimefrgm729k8enqrir/28S662D_sh_19.pdf?rlkey=qvyip7rjqfy6i9yegqrt57n23&dl=0
>

Ok that doesn't surprise me.
I'd want to be sure that the requirement is always met even when the 12V 
connector is in a position where it isn't sure whether it's connected or 
not.
Or rapid and repeated connect/disconnect of 12V doesn't cause any issue.