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From: john larkin <jl@650pot.com>
Newsgroups: sci.electronics.design
Subject: Re: Anticipating processor architectural evolution
Date: Mon, 29 Apr 2024 15:32:47 -0700
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On Sat, 27 Apr 2024 16:11:30 -0700, Don Y
<blockedofcourse@foo.invalid> wrote:

>I've had to refactor my RTOS design to accommodate the likelihood of SMT
>in future architectures.
>
>Thinking (hoping?) these logical cores to be the "closest to the code",
>I call them "Processors" (hysterical raisins).  Implicit in SMT is the
>notion that they are architecturally similar/identical.
>
>These are part of PHYSICAL cores -- that I appropriately call "Cores".
>
>These Cores are part of "Hosts" (ick; term begs for clarity!)... what
>one would casually call "chips"/CPUs.  Note that a host can house dissimilar
>Cores (e.g., big.LITTLE).
>
>Two or more hosts can be present on a "Node" (the smallest unit intended to
>be added to or removed from a "System").  Again, they can be dissimilar
>(think CPU/GPU).
>
>I believe this covers the composition/hierarchy of any (near) future
>system architectures.  And, places the minimum constraints on said.
>
>Are there any other significant developments in the pipeline that
>could alter my conception of future hardware designs?

Vaguely related:

https://www.theregister.com/2023/10/30/arm_intel_comment/