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From: Don Y <blockedofcourse@foo.invalid>
Newsgroups: sci.electronics.design
Subject: Re: Zilog stopping Z80 production
Date: Tue, 23 Apr 2024 19:00:00 -0700
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On 4/23/2024 5:08 PM, Edward Rawde wrote:
> It must be trivial to get a VHDL/Verilog model and make your own by now.

The problem with all the early/simple/trivial processors is getting
the rest of the system to run as fast as the core can.  E.g., running
a core at ~200MHz and expecting the same bus timing means < 5ns memory.

(for a Z80, that would be ~10ns as the bus timing is inherently slower)

The better option is to embed the core *in* a design to give you
the advantages of a programmable sequencer (instead of "junk logic")

> The 6809 was my preference but took a few more years.