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From: Bill Sloman <bill.sloman@ieee.org>
Newsgroups: sci.electronics.design
Subject: Re: fast NPN in LT Spice
Date: Fri, 7 Jun 2024 02:58:40 +1000
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On 7/06/2024 2:02 am, john larkin wrote:
> On Wed, 05 Jun 2024 23:46:24 -0400, legg <legg@nospam.magma.ca> wrote:
> 
>> On Tue, 4 Jun 2024 00:10:32 +1000, Bill Sloman <bill.sloman@ieee.org>
>> wrote:
>> <snip>
>>>> Gosh, what a hideous mess, in many respects.
>>>
>>> Do tell us why. You do claim to revel in electronic discussion.
>>
>> Perhaps its the nonlinearity of the output stage, which is biased off.
> 
> I believe that a Spice model should be treated as an engineering
> document: visible title, author, and correct latest-edit date, and it
> should be neatly drawn, with coherent comments where appropriate. It
> should be obvious where the inputs and outputs are, and important
> nodes should have useful net names.
> 
> Versions should be identifiable as such.

If they are part of production documentation, all this goes without saying.

If we are posting a simple circuit here to make a point, it is less 
obvious that we need to conform to your production  standards.

What I posted was a very simple four transistor circuit - two fast NPNs 
arranged as an emitter-coupled 30nsec monostable and a slower 
long-tailed pair level shifter to turn the output into an  ECL-level pulse.

Anybody who has done discrete transistor design should have been able to 
parse it by looking at it.

The only messy object in the diagram was the Spice directive defining 
the BFR92a Spice model, and the only reason I posted the .asc file was 
to provide an example of that approach in action.

I've no idea why I put the sim together - it's paired with a bare 
two-BFR92a emitter coupled monostable sim where the components were 
strung between +5V and and -5V rails. The real life examples it was 
probably drawn from had a +5V rail for the old TTL and a -4.5V rail for 
the old ECL, though I did some work with the Gigabit Logic's GaAs parts 
that needed two negative rails, -3.3V and -5.2V which was a real pain, 
but that was just before ECLinPs and if you needed the speed, that was 
what it took.

> A sim should be useful days or years after it's started. We often have
> a README.txt file alongside the .asc files to explain the situation.

You shouldn't have needed a README.txt file to tell you how to parse 
that circuit.

> Most amateur Spice sims are messy tangled horrors.

If you can't parse a circuit diagram, it always looks like a messy 
tangled horror, and anything complicated always takes a certain amount 
of inspection before it starts making sense.

If you though that what I posted was a "messy tangled horror" you are at 
the "cat sat on the mat" level of schematic reading.

-- 
Bill Sloman, Sydney



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