Path: ...!weretis.net!feeder8.news.weretis.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: "Fred. Zwarts" Newsgroups: comp.theory,sci.logic Subject: Re: Simulating termination analyzers for dummies Date: Wed, 19 Jun 2024 15:56:55 +0200 Organization: A noiseless patient Spider Lines: 146 Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Wed, 19 Jun 2024 15:56:56 +0200 (CEST) Injection-Info: dont-email.me; posting-host="f73c32778335b0321bd1b04b79c4c70c"; logging-data="2094472"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+O7ojBPHnhBqjk/x+C2Nbu" User-Agent: Mozilla Thunderbird Cancel-Lock: sha1:DcyyX2PYS8JtxvD+ZAIaP1SrVQk= Content-Language: en-GB In-Reply-To: Bytes: 8032 Op 19.jun.2024 om 15:00 schreef olcott: > On 6/19/2024 3:08 AM, Fred. Zwarts wrote: >> Op 18.jun.2024 om 18:26 schreef olcott: >>> On 6/18/2024 10:47 AM, Fred. Zwarts wrote: >>>> Op 18.jun.2024 om 17:33 schreef olcott: >>>>> On 6/18/2024 10:20 AM, Fred. Zwarts wrote: >>>>> >>>>> It is a verified fact that serious C people have recently >>>>> agreed to the following verbatim statement in the C group. >>> >>> http://al.howardknight.net/?STYPE=msgid&MSGI=%3Cv4pg5p%24morv%241%40raubtier-asyl.eternal-september.org%3E+ >>> >>>>> You either lack this degree of skill in C or are only >>>>> interested in playing head games. >>>> >>>> I have seen the response. It was most certainly not a serious reply. >>>> But you know apparently to little of C to understand that. >>>> Probably, because you are unable to escape from rebuttal mode, even >>>> if the truth is obvious. >>>> >>> >>> I have known C since K&R was the standard and met >>> Bjarne Stroustrup when he came to our university >>> to promote his new C++ programming language. >>> >>> *You seem to be willfully ignorant* >>> >>>> It was your own proof that showed that in >>>> >>>>         int main() >>>>         { >>>>           return H(main); >>>>         } >>>> >>>> >>>> main halts, whereas H reported non-halting. So, it you were honest >>>> you would stop claiming that H is correct. >>>> >>> >>> That is merely a more difficult to understand version of this >>> same pathological relationship. >>> >>> int main() >>> { >>>    Output("Input_Halts = ", HH0(main)); >>> } >>> >>> _main() >>> [000020c2] 55         push ebp >>> [000020c3] 8bec       mov ebp,esp >>> [000020c5] 68c2200000 push 000020c2 ; push main >>> [000020ca] e833f4ffff call 00001502 ; call HH0 >>> [000020cf] 83c404     add esp,+04 >>> [000020d2] 50         push eax >>> [000020d3] 6843070000 push 00000743 >>> [000020d8] e885e6ffff call 00000762 >>> [000020dd] 83c408     add esp,+08 >>> [000020e0] eb04       jmp 000020e6 >>> [000020e2] 33c0       xor eax,eax >>> [000020e4] eb02       jmp 000020e8 >>> [000020e6] 33c0       xor eax,eax >>> [000020e8] 5d         pop ebp >>> [000020e9] c3         ret >>> Size in bytes:(0040) [000020e9] >>> >>>   machine   stack     stack     machine    assembly >>>   address   address   data      code       language >>>   ========  ========  ========  =========  ============= >>> [000020c2][001036c3][00000000] 55         push ebp >>> [000020c3][001036c3][00000000] 8bec       mov ebp,esp >>> [000020c5][001036bf][000020c2] 68c2200000 push 000020c2 ; push main >>> [000020ca][001036bb][000020cf] e833f4ffff call 00001502 ; call HH0 >>> New slave_stack at:103767 >>> >>> Begin Local Halt Decider Simulation   Execution Trace Stored at:11376f >>> [000020c2][0011375f][00113763] 55         push ebp      ; begin main >>> [000020c3][0011375f][00113763] 8bec       mov ebp,esp >>> [000020c5][0011375b][000020c2] 68c2200000 push 000020c2 ; push main >>> [000020ca][00113757][000020cf] e833f4ffff call 00001502 ; call HH0 >>> New slave_stack at:14e18f >>> [000020c2][0015e187][0015e18b] 55         push ebp      ; begin main >>> [000020c3][0015e187][0015e18b] 8bec       mov ebp,esp >>> [000020c5][0015e183][000020c2] 68c2200000 push 000020c2 ; push main >>> [000020ca][0015e17f][000020cf] e833f4ffff call 00001502 ; call HH0 >>> Local Halt Decider: Infinite Recursion Detected Simulation Stopped >>> >>> [000020cf][001036c3][00000000] 83c404     add esp,+04 >>> [000020d2][001036bf][00000000] 50         push eax >>> [000020d3][001036bb][00000743] 6843070000 push 00000743 >>> [000020d8][001036bb][00000743] e885e6ffff call 00000762 >>> Input_Halts = 0 >>> [000020dd][001036c3][00000000] 83c408     add esp,+08 >>> [000020e0][001036c3][00000000] eb04       jmp 000020e6 >>> [000020e6][001036c3][00000000] 33c0       xor eax,eax >>> [000020e8][001036c7][00000018] 5d         pop ebp >>> [000020e9][001036cb][00000000] c3         ret           ; exit main >>> Number of Instructions Executed(10070) == 150 Pages >>> >> >> It is easier to understand because a print statement was added. >> You proved that it halts, but H0 reports non-halting. >> So, it produces a false negative. >> So, now it has been proved that H, H0, etc produce false negatives, >> when used to determine halting behaviour, please, stop to call them >> halt-deciders, or termination-deciders. >> They might be "simulation deciders". When returning true, the >> simulation was correct, when false, the full simulation was not possible. > > I don't want to discuss your screwy example because I > can't use screwy examples in my paper. > > void DDD() > { >   H0(DDD); > } > > _DDD() > [000020a2] 55         push ebp      ; housekeeping > [000020a3] 8bec       mov ebp,esp   ; housekeeping > [000020a5] 68a2200000 push 000020a2 ; push DDD > [000020aa] e8f3f9ffff call 00001aa2 ; call H0 > [000020af] 83c404     add esp,+04   ; housekeeping > [000020b2] 5d         pop ebp       ; housekeeping > [000020b3] c3         ret           ; never gets here > Size in bytes:(0018) [000020b3] > > Exactly which step of DDD emulated by H0 was emulated > incorrectly such that this emulation would be complete? > AKA DDD emulated by H0 reaches machine address [000020b3] > Yes, that is your attitude. An example that proves you are wrong are called 'screwy'. You prefer more complex examples, for which you can easier hide the essential details. Similarly, it has been pointed out to you many times that your simulation fails with the call instruction at 000020aa. H0 is required to halt, but the simulator fails to simulate the 'ret' instruction of H0. The simulated H0 is aborted one cycle before it would reach its 'ret' instruction, after which the simulation would proceed with 000020af. Your problem is that H0 (or any other simulator you have shown) is able to simulate itself up to its simulated 'ret'. It seem that you know it, because you never denied it. This simple fact seems already to be over your head, so, you prefer to ignore or to forget it and just repeat the baseless claim.