Path: ...!news.nobody.at!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.arch Subject: Instruction counts (was: Decrement And Branch) Date: Fri, 16 Aug 2024 05:23:30 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 48 Message-ID: <2024Aug16.072330@mips.complang.tuwien.ac.at> References: <2024Aug14.111001@mips.complang.tuwien.ac.at> <2024Aug15.123928@mips.complang.tuwien.ac.at> <1f9360728a7b19bcbf3660565adfa2f5@www.novabbs.org> Injection-Date: Fri, 16 Aug 2024 08:11:08 +0200 (CEST) Injection-Info: dont-email.me; posting-host="f685176504da3451b219cd11a88d6053"; logging-data="1419384"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+b9lifDVD8g0yjsm4vtI/m" Cancel-Lock: sha1:jUaiSU9FKKQGQAtgQsL/XoahD+Q= X-newsreader: xrn 10.11 Bytes: 2902 mitchalsup@aol.com (MitchAlsup1) writes: >And RISC-V ends up with over 448 instructions How do you count this? Looking at chapter 19 of https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf, I count for RV64G: 47 RV32I 15 RV64I additional instructions 8 RV32M 5 RV64M additional instructions 11 RV32A 11 RV64A additional instructions 26 RV32F 4 RV64F additional instructions 26 RV32D 6 RV64D additional instructions --------------------------------- 159 RV64G >whereas My 66000 has but 65. There are also One-instruction set computer designs , and by that metric they are the best, no? The main thing I dislike about Celio's talk and work is that he uses the same metric for advocating his approach without giving any reason why it should be relevant. He also makes the mistake of using instruction count for discerning between RISC and non-RISC (which would make the PDP-11, 6502 and probably 8086 more RISC than RV64G) instead of using John Masheys approach of identifying common traits; and instruction count was not among the criteria that John Mashey identified as discerning between RISC and non-RISC (not surprising given non-RISCs like PDP-11). Patterson (who is also on that paper and who failed to define RISC when he wrote the papers that introduced the term) makes the same mistake when arguing for his vector approach (which, I think, resulted in RV64V) over the approach taken in, e.g., AVX512. So maybe Celio just was Patterson's voice in his talk, but he appeared to speak his conviction. - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup,