Path: ...!weretis.net!feeder9.news.weretis.net!news.nk.ca!rocksolid2!i2pn2.org!.POSTED!not-for-mail From: mitchalsup@aol.com (MitchAlsup1) Newsgroups: comp.arch Subject: Re: My 66000 and High word facility Date: Mon, 19 Aug 2024 19:31:54 +0000 Organization: Rocksolid Light Message-ID: References: <38055f09c5d32ab77b9e3f1c7b979fb4@www.novabbs.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: i2pn2.org; logging-data="3151626"; mail-complaints-to="usenet@i2pn2.org"; posting-account="65wTazMNTleAJDh/pRqmKE7ADni/0wesT78+pyiDW8A"; User-Agent: Rocksolid Light X-Spam-Checker-Version: SpamAssassin 4.0.0 X-Rslight-Site: $2y$10$rAN67CULoQDi5TWQuEejkORQYLdXzm5QygtQvTb5Wdr1UM97VrY5W X-Rslight-Posting-User: ac58ceb75ea22753186dae54d967fed894c3dce8 Bytes: 2693 Lines: 37 On Mon, 19 Aug 2024 18:52:39 +0000, Brett wrote: > MitchAlsup1 wrote: >> On Sun, 11 Aug 2024 0:46:09 +0000, Brett wrote: >> >> >> The thing is that one you go down the GBOoO route, your lack of >> registers >> "namable in ASM" ceases to become a performance degrader. With renaming >> one can have R7 in use 40 times in a 100 instruction deep execution >> window. > > If this was true we would have 16 or even 8 visible registers, and all > would be fine. x86 does mostly fine with 16, of course x84 had fab and > cubic dollar advantages that dwarfed the register limit. Careful, here:: x86 has LD-OPs and LD-OP-STs which makes the 16 register file feel more like it has 20-22 registers. Do not underestimate this phenomenon. The gain from 16-32 registers is only 3%-ish so one would estimate that 22 registers would have already gained 1/2 of all of what is possible. > 64 separate registers was a bridge to far, but it was an interesting > exercise before it crashed and burned due to the bits being not quite > available. So close, yet so far. I could not make it work. We remain hobbled by the definition of Byte containing exactly 8-bits. It is this which drives the 16-bit and 32-bit instruction sizes; and it is this which drives the sizes of constants used by the instruction stream. 64 registers makes PERFECT sense in a 36-bit (or 72-bit) architecture. But we must all face facts:: a) Little Endian Won b) 8-bit Bytes Won c) longer operands are composed of multiple bytes mostly powers of 2. d) otherwise it is merely an academic exercise.