Path: ...!news.nobody.at!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: David Brown Newsgroups: comp.arch Subject: Re: Computer architects leaving Intel... Date: Fri, 30 Aug 2024 18:33:40 +0200 Organization: A noiseless patient Spider Lines: 46 Message-ID: References: <2024Aug29.151755@mips.complang.tuwien.ac.at> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 30 Aug 2024 18:33:40 +0200 (CEST) Injection-Info: dont-email.me; posting-host="3b8d9008b438dc7a1af6ab394661d0db"; logging-data="603243"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/UC8aYluB5eWrcWRmociHji4LtNJyHjqM=" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Cancel-Lock: sha1:lz7G1JlG2sV2/xB4vtI9n8pXWLg= In-Reply-To: Content-Language: en-GB Bytes: 3046 On 30/08/2024 17:44, Scott Lurndal wrote: > jgd@cix.co.uk (John Dallman) writes: >> In article <2024Aug29.151755@mips.complang.tuwien.ac.at>, >> anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote: >>> jgd@cix.co.uk (John Dallman) writes: >>>> Android is apparently waiting for a new RISC-V instruction set >>>> extension; >>> Which one? >> >> I don't know what its name is. It was proposed by Hans Boehm, and the >> Android team pointed me to this discussion on a RISC-V mailing list: >> >> https://lists.riscv.org/g/tech-unprivileged/topic/92916241 >> >> Searching with various terms suggests it might well be the Zabha >> extension, ratified in April this year, but that is deduction. >> >>> You may not consider it large-scale, but we wanted to have two >>> RISC-V servers for teaching (in particular, for the compiler >>> course). >> >> Makes sense. It is not in itself "large-scale," but suitable hardware is >> only going to be available if someone wants a lot of it, enough to make >> building it worthwhile. >> >>> Now it's two years later, and the RISC-V servers are still not >>> showing up. >> >> Yup. RISC-V established a lot of awareness, and some expectations, but >> there hasn't been the equipment to let people start using it. > > I expect RISC-V to gradually encroach on the embedded market and as > microcontroller IP that can be included in SoC accelerators (primarily > to avoid license fees for the alternatives such as cortex m7). > That's where I expect to see it, and I hope to see more of it. At the very least, decent competition will help push ARM forward. What I personally would like to see is RISC-V extensions aimed at real-time and deterministic systems - RTOS acceleration, hardware semaphores, and the like. > I don't see it replacing ARM64, X86_64/AMD64 or other server-grade > processors.