Path: ...!2.eu.feeder.erje.net!feeder.erje.net!newsfeed.bofh.team!paganini.bofh.team!not-for-mail From: Waldek Hebisch Newsgroups: comp.lang.c Subject: Re: Top 10 most common hard skills listed on resumes... Date: Sun, 8 Sep 2024 21:34:27 -0000 (UTC) Organization: To protect and to server Message-ID: References: <20240828134956.00006aa3@yahoo.com> Injection-Date: Sun, 8 Sep 2024 21:34:27 -0000 (UTC) Injection-Info: paganini.bofh.team; logging-data="2366048"; posting-host="WwiNTD3IIceGeoS5hCc4+A.user.paganini.bofh.team"; mail-complaints-to="usenet@bofh.team"; posting-account="9dIQLXBM7WM9KzA+yjdR4A"; User-Agent: tin/2.6.2-20221225 ("Pittyvaich") (Linux/6.1.0-9-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.9.3 Bytes: 2612 Lines: 25 David Brown wrote: > > And while microcontrollers sometimes have a limited form of branch > prediction (such as prefetching the target from cache), the more > numerous and smaller devices don't even have instruction caches. > Certainly none of them have register renaming or speculative execution. IIUC STM4 series has cache, and some of them are not so big. There are now several chinese variants of STM32F103 and some of them have caches (some very small like 32 words, IIRC one has 8 words and it is hard to decide if this very small cache or big prefetch buffer). A notable example is MH32F103. Base model officially has 64kB RAM and 256KB flash. AFAIK this flash is rather slow SPI flash. It also has 16kB cache which probably is 4-way set associative with few extra lines (probably 4) to increase apparent associativity. I write probably because this is result of reasoning based on several time measurements. If you hit cache it runs nicely at 216 MHz. Cache miss costs around 100 clocks (varies depending on exact setting of timing parameters and form of access). Similar technology seem to be popular among chines chip makers, especially for "bigger" chips. But IIUC GD use is for chips of size of STM32F103C8T6. -- Waldek Hebisch