Path: ...!news.mixmin.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Michael S Newsgroups: comp.arch Subject: Re: Is Intel exceptionally unsuccessful as an architecture designer? Date: Tue, 24 Sep 2024 12:49:44 +0300 Organization: A noiseless patient Spider Lines: 61 Message-ID: <20240924124944.00006d86@yahoo.com> References: <21028ed32d20f0eea9a754fafdb64e45@www.novabbs.org> <20240918190027.00003e4e@yahoo.com> <920c561c4e39e91d3730b6aab103459b@www.novabbs.org> <%dAHO.54667$S9Vb.39628@fx45.iad> <4f84910a01d7db353eedadd7c471d7d3@www.novabbs.org> <20240923105336.0000119b@yahoo.com> <6577e60bd63883d1a7bd51c717531f38@www.novabbs.org> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Tue, 24 Sep 2024 11:49:17 +0200 (CEST) Injection-Info: dont-email.me; posting-host="b1fade10e8a2bab21410dad877002ecd"; logging-data="3291197"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19P4pkjJBWlYUKNcrFsEi92duh0bRareq4=" Cancel-Lock: sha1:EXoN66OmBTqsT4a/BGZW0zWpyb8= X-Newsreader: Claws Mail 3.19.1 (GTK+ 2.24.33; x86_64-w64-mingw32) Bytes: 4099 On Mon, 23 Sep 2024 20:59:42 +0000 mitchalsup@aol.com (MitchAlsup1) wrote: > On Mon, 23 Sep 2024 7:53:36 +0000, Michael S wrote: > > > On Mon, 23 Sep 2024 01:34:55 +0000 > > mitchalsup@aol.com (MitchAlsup1) wrote: > > > >> On Mon, 23 Sep 2024 0:53:35 +0000, jseigh wrote: > >> > >>> On 9/22/2024 5:39 PM, MitchAlsup1 wrote: > >> > >>> Speaking of memory models, remember when x86 didn't have > >>> a formal memory model. They didn't put one in until > >>> after itanium. Before that it was a sort of processor > >>> consistency type 2 which was a real impedance mismatch > >>> with what most concurrent software used a a memory model. > >> > >> When only 1 x86 would fit on a die, it really did not mater > >> much. I was at AMD when they were designing their memory > >> model. > >> > >>> Joe Seigh > > > > > > Why # of CPU cores on die is of particular importance? > > Prior to multi-CPUs on a die; 99% of all x86 systems were > mono-CPU systems, and the necessity of having a well known > memory model was more vague. > Although there were servers > with multiple CPUs in them they represented "an afternoon > in the FAB" compared to the PC oriented x86s. > Even if 99% is correct, there were still 6-7 figures worth of dual-processor x86 systems sold each year and starting from 1997 at least tens of thousands of quads. Absence of ordering definitions should have been a problem for a lot of people. But somehow, it was not. > That is "we did not see the problem until it hit us in > the face." Once it did, we understood what we had to do: > presto memory model. > > Also note: this was just after the execution pipeline went > Great Big Our of Order, and thus made the lack of order > problems much more visible to applications. {Pentium Pro} > And that happened almost 10 years before Intel published their first official x86 Memory Ordering paper. As to AMD, I think they hold it unpublished even longer. > > According to my understanding, what matters is # of CPU cores with > > coherent access to the same memory+IO. > > For x86, 4 cores (CPUs) were relatively common since 1996. There > > existed few odd 8-core systems too, still back in the last century. > >