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From: "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com>
Newsgroups: comp.arch
Subject: Re: Is Intel exceptionally unsuccessful as an architecture designer?
Date: Sat, 21 Sep 2024 13:26:13 -0700
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On 9/21/2024 6:54 AM, Scott Lurndal wrote:
> mitchalsup@aol.com (MitchAlsup1) writes:
>> On Sat, 21 Sep 2024 1:12:38 +0000, Brett wrote:
>>
>>> MitchAlsup1 <mitchalsup@aol.com> wrote:
>>>> On Fri, 20 Sep 2024 21:54:36 +0000, Chris M. Thomasson wrote:
> 
>>> This could be fine if you are going for the AI market of slow AI cpu
>>> with huge memory and bandwidth.
>>>
>>> The AI market is bigger than the general server market as seen in
>>> NVidea’s sales.
>>>
>>>> Bus interconnects are not setup to take a CPU cache miss from one
>>>> DRAM to a different DRAM on behalf of its contained CPU(s).
>>>> {Chicken and egg problem}
>>
>> Thus a problem with the CPU on DRAM approach.
>>
>>> Such a dram would be on the PCIE busses, and the main CPU’s would barely
>>> touch that ram, and the AI only searches locally.
>>
>> Better make it PCIe+CXL so the downstream CPU is cache coherent.
> 
> Exactly.
> 
> https://www.marvell.com/products/cxl.html

What about a weak coherency where a programmer has to use the correct 
membars to get the coherency required for their specific needs? Along 
the lines of UltraSPARC in RMO mode?