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From: mitchalsup@aol.com (MitchAlsup1)
Newsgroups: comp.arch
Subject: Re: Tonights Tradeoff - Carry and Overflow
Date: Sat, 12 Oct 2024 18:50:35 +0000
Organization: Rocksolid Light
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On Sat, 12 Oct 2024 9:38:01 +0000, Robert Finch wrote:

> On 2024-10-09 6:44 a.m., Robert Finch wrote:
> Mulled over carry and overflow in arithmetic operations. Looked at
> widening the datapath to 66-bits to hold carry and overflow bits.
> Thinking it may increase the size of the design by over 3% just to
> support carry and overflow. For now, an instruction, ADDGC, was added to
> generate the carry bit as a result. A 256-bit add looks like:
>
> ; 256 bit add
> ; A = r1,r2,r3,r4
> ; B = r5,r6,r7,r8
> ; S = r9,r10,r11,r12
>
> 	add r9,r1,r5,r0
> 	addgc r13,r1,r5,r0
> 	add r10,r2,r6,r13
> 	addgc r13,r2,r6,r13
> 	add r11,r7,r3,r13
> 	addgc r13,r7,r3,r13
> 	add r12,r8,r4,r13

My 66000 version::

       CARRY   R8,{{IO}{IO}{IO}{O}}
       ADD     R4,R12,R16
       ADD     R5,R13,R17
       ADD     R6,R14,R18
       ADD     R7,R15,R19
            // R{8,7,6,5,4} contain the 257-bit result.

256-bit add giving 257-bit result.
>
> Not very elegant a solution, but it is simple. I think it requires
> minimal hardware. Three input ADD is already present and ADDGC just
> routes the carry bit to the output.