Path: ...!3.eu.feeder.erje.net!feeder.erje.net!news.in-chemnitz.de!news.swapon.de!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: "Chris M. Thomasson" Newsgroups: comp.arch Subject: Re: Is Intel exceptionally unsuccessful as an architecture designer? Date: Mon, 23 Sep 2024 14:35:53 -0700 Organization: A noiseless patient Spider Lines: 53 Message-ID: References: <21028ed32d20f0eea9a754fafdb64e45@www.novabbs.org> <20240918190027.00003e4e@yahoo.com> <920c561c4e39e91d3730b6aab103459b@www.novabbs.org> <%dAHO.54667$S9Vb.39628@fx45.iad> <4f84910a01d7db353eedadd7c471d7d3@www.novabbs.org> <20240923105336.0000119b@yahoo.com> <6577e60bd63883d1a7bd51c717531f38@www.novabbs.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 23 Sep 2024 23:35:55 +0200 (CEST) Injection-Info: dont-email.me; posting-host="57077e43f9083b2c8af43c64109cbf78"; logging-data="3016525"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18GY8pUvl4ONZNdtJx3jL/nallVw1UCuVk=" User-Agent: Mozilla Thunderbird Cancel-Lock: sha1:Gm002fWeer2P18gdttay3xGMZcs= In-Reply-To: <6577e60bd63883d1a7bd51c717531f38@www.novabbs.org> Content-Language: en-US Bytes: 4090 On 9/23/2024 1:59 PM, MitchAlsup1 wrote: > On Mon, 23 Sep 2024 7:53:36 +0000, Michael S wrote: > >> On Mon, 23 Sep 2024 01:34:55 +0000 >> mitchalsup@aol.com (MitchAlsup1) wrote: >> >>> On Mon, 23 Sep 2024 0:53:35 +0000, jseigh wrote: >>> >>>> On 9/22/2024 5:39 PM, MitchAlsup1 wrote: >>> >>>> Speaking of memory models, remember when x86 didn't have >>>> a formal memory model.  They didn't put one in until >>>> after itanium.  Before that it was a sort of processor >>>> consistency type 2 which was a real impedance mismatch >>>> with what most concurrent software used a a memory model. >>> >>> When only 1 x86 would fit on a die, it really did not mater >>> much. I was at AMD when they were designing their memory >>> model. >>> >>>> Joe Seigh >> >> >> Why # of CPU cores on die is of particular importance? > > Prior to multi-CPUs on a die; 99% of all x86 systems were > mono-CPU systems, and the necessity of having a well known > memory model was more vague. Although there were servers > with multiple CPUs in them they represented "an afternoon > in the FAB" compared to the PC oriented x86s. > > That is "we did not see the problem until it hit us in > the face." Once it did, we understood what we had to do: > presto memory model. > > Also note: this was just after the execution pipeline went > Great Big Our of Order, and thus made the lack of order > problems much more visible to applications. {Pentium Pro} Iirc, been a while, I think there was a problem on one of the Pentiums, might be the pro, where it had an issue with releasing a spinlock with a normal store. I am most likely misremembering, but it is sparking some strange memories. Way back on c.p.t, Alex Terekhov (hope I did not butcher the spelling of his name), anyway, wrote about it, I think... Way back. early 2000's I think. > >> According to my understanding, what matters is # of CPU cores with >> coherent access to the same memory+IO. >> For x86, 4 cores (CPUs) were relatively common since 1996. There >> existed few odd 8-core systems too, still back in the last century.