Path: news.eternal-september.org!eternal-september.org!.POSTED!not-for-mail
From: Stephen Fuld <sfuld@alumni.cmu.edu.invalid>
Newsgroups: comp.arch
Subject: Re: Why I've Dropped In
Date: Tue, 17 Jun 2025 11:09:33 -0700
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On 6/17/2025 10:45 AM, MitchAlsup1 wrote:
> On Tue, 17 Jun 2025 1:26:01 +0000, Stephen Fuld wrote:
> 
>> On 6/16/2025 9:17 AM, Stefan Monnier wrote:
>>>>> Therefore, I reduced the index register and base register fields to
>>>>> three bits each, using only some of the 32 integer registers for those
>>>>> purposes.
>>>> This is going to hurt register allocation.
>>>
>>> I vaguely remember reading somewhere that it doesn't have to be too bad:
>>> e.g. if you reduce register-specifiers to just 4bits for a 32-register
>>> architecture and kind of "randomize" which of the 16 values refer to
>>> which of the 32 registers for each instruction, it's fairly easy to
>>> adjust a register allocator to handle this correctly (assuming you
>>> choose your instructions beforehand, you simply mark, for each
>>> instructions, the unusable registers as "interfering"), and the end
>>> result is often almost as good as if you had 5bits to specify
>>> the registers.
>>
>> I can see that it isn't too hard on the logic for the register
>> allocator,
> 
> You are missing the BIG problem::
> 
> Register allocator allocated Rk for calculation j and later allocates
> Rm for instruction p, then a few instructions later the code generator
> notices that Rk and RM need to be paired or shared and they were not
> originally. How does on fix this kind of problem without adding more
> passes over the intermediate representation ??

Good point.  Thanks.


> 
>>            but I suspect it will lead to more register saving and
>> restoring.
> 
> And reg-reg MOVment.

Yes.  I should have mentioned that as well.



-- 
  - Stephen Fuld
(e-mail address disguised to prevent spam)