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From: Gerhard Hoffmann <dk4xp@arcor.de>
Newsgroups: sci.electronics.design
Subject: Re: New ISA board to play with transputers
Date: Sun, 6 Jul 2025 11:37:54 +0200
Message-ID: <104dg5i$1r2fl$1@solani.org>
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In-Reply-To: <104d444$20js8$1@dont-email.me>

Am 06.07.25 um 08:12 schrieb Don Y:
> On 7/4/2025 3:30 PM, Oscar Toledo G. wrote:
>> I've developed an ISA board to test some transputer boards (TRAM) I 
>> bought in
>> eBay, I started with a prototype wired board on an ISA development 
>> card, and then I made a proper PCB in three iterations as I solved 
>> some bugs.
>>
>> The ISA connector was just because I have several old PC motherboards 
>> (80286,
>> 80486, a Pentium MMX, and a AMD K5)
>>
>> The history of development is available at
>> https://nanochess.org/transputer_board.html
>>
>> The schematics and PCB are available at
>> https://github.com/nanochess/transputer/pcb
>>
>> In the same git you can get my operating system developed in 1993-1996.
> 
> Excellent!  What did you learn from the experience (besides the
> perils of rushing a PCB)?  I.e., what value (or lack thereof) did the
> transputer offer?
> 
> Could you, perhaps, have used a small SBC (arduino, rPi, etc.) and
> used GPIOs to twiddle the hardware -- and a USB interface to talk
> to it?  Or, was the ISA bus an important asset?

In a previous life I had quite huge a T800 Tranputer cluster and also
did some designs that connected to it.
The ISA bus was not important, but there was a link adaptor
chip (C11?  - where is my bottle of Gerontol Forte?) that had a
SRAM-alike "foreign" side that made it easy to handle.

In
< 
https://www.flickr.com/photos/137684711@N07/52631074700/in/datetaken/lightbox/ 
  >
the link chip is between the Western Digital SCSI controller and the
VLSI serial/par IO chip.

Complete industrial PC/AT with Multibus2, lots of DRAM, disks, floppy, 
.... Thanks Goddess I had someone to do the board layout in DOS Orcad STD
on a Compaq 286  :-)

Occam was fun. Maybe nowadays it would make a bigger impact with a
substantial number of CPUs on a chip.

Cheers, Gerhard