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From: John Savard <quadibloc@invalid.invalid>
Newsgroups: comp.arch
Subject: Re: Why I've Dropped In
Date: Tue, 22 Jul 2025 04:30:28 -0000 (UTC)
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On Tue, 10 Jun 2025 22:53:27 +0000, quadibloc wrote:

> Include pairs of short instructions as part of the ISA, but make the
> short instructions 14 bits long instead of 15 so they get only 1/16 of
> the opcode space. This way, the compromise is placed in something that's
> less important. In the CISC mode, 17-bit short instructions will still
> be present, after all.

After this change, I have been busily making minor tweaks to the ISA.

The latest one involved a header format which allowed room for fourteen
alternate 17-bit short instructions in a block, in order to permit
a higher level of superscalar operation.

I made opcode space for this header by using two opcodes from the standard
memory-reference instruction set for it; they were the ones formerly used
for load address and jump to subroutine with offset.

I was not happy with doing this, however. Right now, I am engaging in a
mighty struggle to squeeze the available opcode space to avoid doing this.
However, try as I may, it may well be that the cost of this will turn out
to be too great. But if I can manage it, a significant restructuring of
the opcodes of this iteration of Concertina II may be coming soon.

John Savard