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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: PCIe MSI-X interrupts
Date: Thu, 27 Jun 2024 11:27:20 +0300
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On Thu, 27 Jun 2024 01:47:49 +0000
mitchalsup@aol.com (MitchAlsup1) wrote:

> 
> Exactly what are you intending to mean from "single-copy atomic
> accesses" ??
> 

It sounds as a politically correct way of saying "default memory
ordering of ARMv8.1-A and later".
I.e. weaker than x86-64 and SPARC TSO, but stronger than Itanium.
Probably stronger than POWER, but I am not sure if POWER ever had memory
ordering model formalized.