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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: Continuations
Date: Thu, 18 Jul 2024 16:16:56 +0300
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On Thu, 18 Jul 2024 06:00:46 -0000 (UTC)
Thomas Koenig <tkoenig@netcologne.de> wrote:

> >  
> 
> What about SIMD width underlying the the VVM implementation?
> All SIMD implementations I know of allow performing floating point
> ops in paralell.  Is it planned that My 66000 can also do that?
> (If not, that would be a big disadvantage for scientific/technical
> work).

All pre-Merom implementation of SSE2, i.e. Intel Pentium 4, Intel
Pentium-M and AMD K8, do not perform double precision floating point
ops in parallel. The same applies to SSE2 implementations on few
post-Merom "small" cores, both from Intel and from AMD.