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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: Continuations
Date: Thu, 18 Jul 2024 16:40:49 +0300
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On Wed, 17 Jul 2024 23:17:37 +0000
mitchalsup@aol.com (MitchAlsup1) wrote:

> 
> A really BIG implementation with 4 FMAC units per core could unroll
> the loop (by reservation stations) such that each iteration would
> still be 44-cycles, but you could run 4 in parallel and achieve 4
> results every 44-cycles--which to most people smells like 1 result
> every 11-cycles.
> 
> {Would be an interesting reservation station design, though}
> >
> >
> >  

Your "really BIG" implementation sound not so big by modern standards.
I think, all x86 cores sold in last 5 years except those that are called
"small" or "economical" have at least 8 FMAC units. The last
mainstream x86 core with 4 FMAC was AMD Zen1.
On the ARM side "mainstream" Cortex-A cores still feature 4 FMAC units,
but "premium" Cortex-X cores have more. So do "performance" cores from
Apple and Qualcomm.