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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: Chipsandcheese article on the CDC6600
Date: Tue, 23 Jul 2024 12:40:32 +0300
Organization: A noiseless patient Spider
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On Tue, 23 Jul 2024 00:21:44 -0000 (UTC)
Lawrence D'Oliveiro <ldo@nz.invalid> wrote:

> On Mon, 22 Jul 2024 17:51:21 +0300, Michael S wrote:
> 
> > On Mon, 22 Jul 2024 13:41:40 +0000 mitchalsup@aol.com (MitchAlsup1)
> > wrote:
> >   
> >> CDC 6600 had a RISC instruction set !!
> >>
> >>  
> > It has RISC-like features, most importantly load-store architecture.
> > Simple instruction formats and only two instruction width options
> > also sound RISCy. But hard coupling between A registers and X
> > registers does not look like RISC to me.  
> 
> RISC-V is adopting a very similar idea, in preference to the
> widespread current SIMD fashion.

WTF are you talking about?
Sounds like you either never read about CDC 6600 instruction set or
completely forgot everything you ever read about it.