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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: Instruction Tracing
Date: Mon, 12 Aug 2024 11:09:18 +0300
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On Mon, 12 Aug 2024 06:33:17 -0000 (UTC)
Lawrence D'Oliveiro <ldo@nz.invalid> wrote:

> On Mon, 12 Aug 2024 05:29:29 GMT, Anton Ertl wrote:
>=20
> > Already the 21064 is two-wide superscalar (1 integer unit, 1 FPU, 1
> > load/store unit, don't remember if the branch unit could run in
> > parallel to the ALU; I think not).  And it has very high clock
> > speeds for its time; it appeared with 150MHz while the competition
> > was like 50MHz (SuperSPARC, superscalar) to 100MHz (MIPS R4000, not
> > superscalar), or, for Power, 62.5MHz in the POWER1++.  But POWER1
> > (without ++) preceded the 21064 by 2 years. =20
>=20
> But in spite of having, say, 2=C2=BD times the clock speed of POWER, Alpha
> was not 2=C2=BD times faster, was it?

Of course not.=20
But Alpha EV4 was single chip vs multiple chips in POWER1 or 3 chips of
contemporary PA-RISC.
More relevant comparison is EV4 vs IBM RSC
https://en.wikipedia.org/wiki/RISC_Single_Chip
I think that EV4 was 3-5 times faster than RSC.

Back in 1992-1993 I was not impressed by speed of RS/6000 model 220
relatively to i486 PCs. Frankly, 220 was running much heavier software
stack.