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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: Instruction Tracing
Date: Mon, 12 Aug 2024 18:14:53 +0300
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On Mon, 12 Aug 2024 08:42:51 -0000 (UTC)
Lawrence D'Oliveiro <ldo@nz.invalid> wrote:

> On Mon, 12 Aug 2024 11:09:18 +0300, Michael S wrote:
>=20
> > On Mon, 12 Aug 2024 06:33:17 -0000 (UTC)
> > Lawrence D'Oliveiro <ldo@nz.invalid> wrote:
> >  =20
> >> But in spite of having, say, 2=C2=BD times the clock speed of POWER,
> >> Alpha was not 2=C2=BD times faster, was it? =20
> >=20
> > Of course not. =20
>=20
> That=E2=80=99s what I mean: it took several clock cycles per instruction,
> contrary to just about every other RISC architecture.

On EV4 simple ALU instructions took 1 cycle , both for throughput and
for latency.=20
Shifts and conditional moves had latency of 2, throughput of 1.=20
Integer multiplier was not pipelined, but few RISC also had it
none-pipelined. Latency of integer multiplier was 19-21 cycles.
On FP side both FADD and FMUL were fully pipelined (T=3D1) and had
latency of 6 cycles.
L1D cache hits were fully pipelined (T=3D1) and had latency of 3 cycles.

So, as long as code/data was fitting in L1 cache, EV4 IPC was not
far behind competition. Relatively to MIPS R4K, may be, even ahead.

Of course, cache misses were relatively more expensive than for much
lower clocked competitors. DEC's solution to that was wide and fast
system bus.