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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: number of registers
Date: Wed, 21 Aug 2024 22:31:01 +0300
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On Wed, 21 Aug 2024 19:13:55 +0000
mitchalsup@aol.com (MitchAlsup1) wrote:

> 
> The LD-OP-STs in Athlon and Opteron had a memory OpCode and
> calculation OpCode, and was performed in such a way that the physical
> address of the LD was used for the ST when its time came. The
> calculation OpCode was an ALU or the IMUL/DIV unit.
>

Are you sure about IMUL/DIV ?
MUL and DIV instructions have no RMW form on x86/i386/AMD64.
OTOH, shifts have.