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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: arm ldxr/stxr vs cas
Date: Mon, 9 Sep 2024 20:49:46 +0300
Organization: A noiseless patient Spider
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Message-ID: <20240909204946.0000411f@yahoo.com>
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On Mon, 09 Sep 2024 15:42:45 GMT
scott@slp53.sl.home (Scott Lurndal) wrote:

> Michael S <already5chosen@yahoo.com> writes:
> >On Sun, 08 Sep 2024 18:32:42 GMT
> >scott@slp53.sl.home (Scott Lurndal) wrote:
> >  
> >> Michael S <already5chosen@yahoo.com> writes:  
> >> >On Sun, 08 Sep 2024 16:10:41 GMT
> >> >scott@slp53.sl.home (Scott Lurndal) wrote:
> >> >    
> >> >> 
> >> >> On AMD processors (and likely intel), if a core cannot acquire
> >> >> a cache line in a a finite time, the core will assert the bus
> >> >> lock to ensure forward progress.
> >> >> 
> >> >> Nothing to do with the operating software;  purely a hardware
> >> >> thing.    
> >> >
> >> >
> >> >I think, on AMD processors made in this century the only cases
> >> >that resort to physical bus lock are 
> >> >A) atomic accesses that cross cache boundary
> >> >B) atomic accesses that address non-cached memory regions    
> >> 
> >> C) A core cannot acquire a cache line in a finite time.  We
> >>    encountered this in 2010 on AMD Opteron processors with
> >>    our HyperTransport connected CXL-like chip (designed in 2005);
> >>    r/t latency could be as high as 800ns to remote memory.
> >>   
> >
> >PathScale Infinipath, I suppose.  
> 
> Actully, no.
> 

Horus?