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Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Michael S <already5chosen@yahoo.com> Newsgroups: comp.arch Subject: Re: is Vax addressing sane today Date: Tue, 10 Sep 2024 12:08:40 +0300 Organization: A noiseless patient Spider Lines: 57 Message-ID: <20240910120840.000071e1@yahoo.com> References: <vbd6b9$g147$1@dont-email.me> <memo.20240905225550.19028d@jgd.cix.co.uk> <2024Sep6.080535@mips.complang.tuwien.ac.at> <vbiftm$ui9$1@gal.iecc.com> <2024Sep8.155511@mips.complang.tuwien.ac.at> <73c6d21457c487c61051ec52fe25ea5d@www.novabbs.org> <vbl3qj$22a2q$1@dont-email.me> <09ce1622b872f0b0fa944e868a8c97be@www.novabbs.org> <vbnisc$2hb59$1@dont-email.me> <2024Sep10.094353@mips.complang.tuwien.ac.at> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Tue, 10 Sep 2024 11:08:18 +0200 (CEST) Injection-Info: dont-email.me; posting-host="f724e564b9b82ba3394a62309ea0ddd4"; logging-data="2041887"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18RisKT3m+SXcp4ax47KOGoie684T/OYFk=" Cancel-Lock: sha1:fe8ecisYRp1zTDZD9otj+bpC+gQ= X-Newsreader: Claws Mail 3.19.1 (GTK+ 2.24.33; x86_64-w64-mingw32) Bytes: 3601 On Tue, 10 Sep 2024 07:43:53 GMT anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote: > Brett <ggtgp@yahoo.com> writes: > >Speaking of complex things, have you looked at Swift output, as it > >checks all operations for overflow? > > > >You could add an exception type for that, saving huge numbers of > >correctly predicted branch instructions. > > > >The future of programming languages is type safe with checks, you > >need to get on that bandwagon early. > > MIPS got on that bandwagon early. It has, e.g., add (which traps on > signed overflow) in addition to addu (which performs modulo > arithmetic). Trapping variants were deprecated in Release 6 of MIPS ISA. >>It has been abandoned and replaced by RISC-V several > years ago. I don't think that "replaced by RISC-V" is a correct description of proceedings. > > Alpha got on that bandwagon early. It's a descendent of MIPS, but it > renamed add into addv, and addu into add. It has been canceled around > the year 2000. > > RISC-V, another descendent of MIPS, has an add instruction that > corresponds to MIPS' addu, and no instruction that corresponds to > MIPS' add. They obviously don't think that there's a bandwagon. Note > that RISC-V was designed after Swift was introduced. > > IA-32 got on that bandwagon early. It has a single-byte instruction > trapv that traps if the overflow flag is set. The AMD64 instruction > set is very similar to the IA-32 instruction set, but one of the few > differences is that the trapv instruction was eliminated, and the > encoding replaced with a REX prefix. The AMD64 architects obviously > don't think that there is a bandwagon. > > Apple has been designing their own silicon for a while, and they have > introduced Swift as their language in 2010. Yet they have not > switched to an architecture like MIPS or Alpha, nor have they designed > their own architecture or architecture extension that includes > instructions like Alpha's addv or IA-32's trapv. Instead, they > switched to ARM A64, which does not have such features, after > introducing Swift in 2010. They obviously don't think that there is > such a bandwagon, either. > > - anton How does Intel MPX fit in your picture?