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Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Michael S <already5chosen@yahoo.com> Newsgroups: comp.arch Subject: Re: Is Intel exceptionally unsuccessful as an architecture designer? Date: Mon, 23 Sep 2024 10:53:36 +0300 Organization: A noiseless patient Spider Lines: 33 Message-ID: <20240923105336.0000119b@yahoo.com> References: <memo.20240913205156.19028s@jgd.cix.co.uk> <vcda96$3p3a7$2@dont-email.me> <21028ed32d20f0eea9a754fafdb64e45@www.novabbs.org> <RECGO.45463$xO0f.22925@fx48.iad> <20240918190027.00003e4e@yahoo.com> <vcfp2q$8glq$5@dont-email.me> <jwv34lumjz7.fsf-monnier+comp.arch@gnu.org> <vckpkg$18k7r$2@dont-email.me> <vckqus$18j12$2@dont-email.me> <920c561c4e39e91d3730b6aab103459b@www.novabbs.org> <vcl6i6$1ad9e$1@dont-email.me> <d3b9fc944f708546e4fbe5909c748ba3@www.novabbs.org> <%dAHO.54667$S9Vb.39628@fx45.iad> <vcna56$1nlod$2@dont-email.me> <a7708487530552a53732070fe08d9458@www.novabbs.org> <vcprkv$2asrd$1@dont-email.me> <e2c993172c11a221c4dcb9973f9cdb86@www.novabbs.org> <vcqe6f$2d8oa$1@dont-email.me> <4f84910a01d7db353eedadd7c471d7d3@www.novabbs.org> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Mon, 23 Sep 2024 09:53:09 +0200 (CEST) Injection-Info: dont-email.me; posting-host="cab753a840778ec8132c28f15b6b440d"; logging-data="2765340"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18geLjWT1DLMUTpV7lLkJi5Wv0X2I0F4sc=" Cancel-Lock: sha1:kP5i9KUDhEDqGpIqUQsW8eY++Gw= X-Newsreader: Claws Mail 3.19.1 (GTK+ 2.24.33; x86_64-w64-mingw32) Bytes: 2695 On Mon, 23 Sep 2024 01:34:55 +0000 mitchalsup@aol.com (MitchAlsup1) wrote: > On Mon, 23 Sep 2024 0:53:35 +0000, jseigh wrote: > > > On 9/22/2024 5:39 PM, MitchAlsup1 wrote: > > > Speaking of memory models, remember when x86 didn't have > > a formal memory model. They didn't put one in until > > after itanium. Before that it was a sort of processor > > consistency type 2 which was a real impedance mismatch > > with what most concurrent software used a a memory model. > > When only 1 x86 would fit on a die, it really did not mater > much. I was at AMD when they were designing their memory > model. > > > Joe Seigh Why # of CPU cores on die is of particular importance? According to my understanding, what matters is # of CPU cores with coherent access to the same memory+IO. For x86, 4 cores (CPUs) were relatively common since 1996. There existed few odd 8-core systems too, still back in the last century.