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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: is Vax addressing sane today
Date: Mon, 7 Oct 2024 22:26:58 +0300
Organization: A noiseless patient Spider
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On Mon, 7 Oct 2024 17:38:54 -0000 (UTC)
Thomas Koenig <tkoenig@netcologne.de> wrote:

> Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
> > Michael S <already5chosen@yahoo.com> writes:  
> >>On Mon, 07 Oct 2024 07:17:02 GMT
> >>anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:
> >>  
> >>> 
> >>> However, in John Mashey's criteria the number of registers plays a
> >>> role; he requires >4 bits for the GPR specifier, and >3 bits for
> >>> the FPR specifier.
> >>> 
> >>> - anton  
> >>
> >>Which sounds rather arbitrary.  
> >
> > In a way it is, but see below.
> >  
> >>Or even worse, like if he wanted for
> >>SPARC to be called 'typical RISC' and for ARM to be called atypical
> >>and had chosen the numbers to match the agenda.  
> >
> > I think that ARM did not exist for John Mashey.  
> 
> When was his definition made?
> 
> ARM was rather late to the RISC game, this might have been literally
> true.

ARM was rather early to the RISC game. Shipped for profit since late
1986. Less than a year after MIPS and ROMP. Several months after
SPARC. PA-RISC first shipped in the 1986H1, but volume production
started later than ARM.
Appolo PRISM, Motorola 88K, Intel i960 and AMD 29K all came later than
ARM.