Path: ...!eternal-september.org!feeder2.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail
From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: Arm ldaxr / stxr loop question
Date: Mon, 11 Nov 2024 16:28:48 +0200
Organization: A noiseless patient Spider
Lines: 49
Message-ID: <20241111162848.00003566@yahoo.com>
References: <vfono1$14l9r$1@dont-email.me>
	<YROdnVIXfKmwYrn6nZ2dnZfqn_GdnZ2d@supernews.com>
	<vg5tf7$3tqmi$2@dont-email.me>
	<vgm0g1$3c2t2$3@dont-email.me>
	<zwwXO.842112$_o_3.379966@fx17.iad>
	<vgm4vj$3d2as$1@dont-email.me>
	<vgm5cb$3d2as$3@dont-email.me>
	<OnzXO.657386$1m96.281665@fx15.iad>
	<TfKXO.658488$1m96.146506@fx15.iad>
	<T99YO.79275$MoU3.7336@fx36.iad>
	<db6fdf85752c2b86affc911a98f1798b@www.novabbs.org>
	<_4oYO.862335$_o_3.103294@fx17.iad>
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit
Injection-Date: Mon, 11 Nov 2024 15:28:04 +0100 (CET)
Injection-Info: dont-email.me; posting-host="27d2b08ef44fc2e1730a79a59a8485c3";
	logging-data="335029"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX188SXvhIV1nO10rnHZButrHAhNp1IDEddw="
Cancel-Lock: sha1:BerZFv4nm8J+yiSOloTduzwofYs=
X-Newsreader: Claws Mail 3.19.1 (GTK+ 2.24.33; x86_64-w64-mingw32)
Bytes: 3262

On Mon, 11 Nov 2024 13:59:22 GMT
scott@slp53.sl.home (Scott Lurndal) wrote:

> mitchalsup@aol.com (MitchAlsup1) writes:
> >On Sun, 10 Nov 2024 21:00:23 +0000, EricP wrote:
> >  
> >> Scott Lurndal wrote:  
> >>> EricP <ThatWouldBeTelling@thevillage.com> writes:  
> >>>> Chris M. Thomasson wrote:  
> >>>>> On 11/8/2024 2:56 PM, Chris M. Thomasson wrote:  
> >>>>>> Perhaps sometime tonight. Is seems like optimistic LL/SC
> >>>>>> instead of pessimistic CAS RMW type of logic?  
> >>>>> LL/SC vs cmpxchg8b?  
> >>>> Arm A64 has LDXP Load Exclusive Pair of registers and
> >>>> STXP Store Exclusive Pair of registers looks like it can be
> >>>> equivalent to cmpxchg16b (aka double-wide compare and swap).  
> >>>
> >>> Aarch64 also has CASP, a 128-bit atomic compare and swap
> >>> instruction.  
> >>
> >> Thanks, I missed that.
> >>
> >> Any idea what is the advantage for them having all these various
> >> LDxxx and STxxx instructions that only seem to combine a LD or ST
> >> with a fence instruction?  
> >
> >The advantage is consuming OpCode space at breathtaking speed.
> >Oh wait...
> >  
> >> Why have
> >> LDAPR Load-Acquire RCpc Register
> >> LDAR Load-Acquire Register
> >> LDLAR LoadLOAcquire Register  
> >
> >Because the memory model was not build with the notion of memory
> >order and that not all ATOMIC events start or end with a
> >recognizable inst- ruction. Having ATOMICs announce their beginning
> >and ending eliminates the need for fencing; even if you keep a
> ><relatively> relaxed memory order model.  
> 
> There are fully atomic instructions,  the load/store exclusives are
> generally there for backward compatability with armv7; the full set
> of atomics (SWP, CAS, Atomic Arithmetic Ops, etc) arrived with
> ARMv8.1.
> 

Also for compatibility with Cortex-A53 which is still a significant
part of installed base.