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From: Michael S <already5chosen@yahoo.com>
Newsgroups: comp.arch
Subject: Re: What is an N-bit machine?
Date: Sat, 30 Nov 2024 22:38:52 +0200
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On Sat, 30 Nov 2024 19:40:17 -0000 (UTC)
John Levine <johnl@taugh.com> wrote:

> According to Stephen Fuld  <sfuld@alumni.cmu.edu.invalid>:
> >> a flag, 0 meant 24 bit addressing, 1 meant 31 bit addressing. That
> >> worked reasonably well although they came up with yet more kludges
> >> to let programs switch among multiple 31-bit address spaces.  
> >
> >Was ESA one of those kludges?  
> 
> I'd say that was the main kludge, with primary and secondary address
> spaces and address registers that worked sort of like segment
> registers paired with the address in each regular register.
> 
> >> These days I'd say the relevant N is the size of arithmetic
> >> registers but a lot of marketers appear to disagree with me.  
> >
> >I tend to agree with you, with the caveat, as Mitch pointed out, of
> >SIMD registers.  But I suspect the term N-bit machine, will soon be
> >a historic relic, as most architectures have converged on 64 bit 
> >arithmetic registers, and with the growth of address spaces seeming
> >to slow down, it will be a long time before anyone goes to 128 bit 
> >(non-SIMD) registers.  
> 
> I get the impression that we will have 32 bit architectures for a very
> long time, since they are smaller and cheaper to implement than 64 bit
> and for a lot of embedded applications they are more than adequate.
> Examples are ARM Cortex-R4 and -R5, high performance 32 bit realtime
> chips.
> 

I agree with conclusions, but not with your examples.
IMHO, the whole ARM Cortex-R series is solution looking for problem. It
could be quite easily replaced by 64-bit A series cores.
Now Cortex-M is completely different story. Here 64-bit cores would not
be appropriate.