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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: Arguments for a sane ISA 6-years later
Date: Thu, 01 Aug 2024 17:10:28 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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BGB <cr88192@gmail.com> writes:
>Some amount of the cases where consistency issues have come up in my 
>case have do do with RAM-backed hardware devices, like the rasterizer 
>module. It has its own internal caches that need to be flushed, and not 
>flushing caches (between this module and CPU) when trying to "transfer" 
>control over things like the framebuffer or Z-buffer, can result in 
>obvious graphical issues (and, texture-corruption doesn't necessarily 
>look good either).

The approach taken on AMD64 CPUs is to have different memory types
(and associated memory type range registers).  Plain DRAM is
write-back cached, but there is also write-through and uncacheable
memory.  For a frame buffer that is read by some hardware that can
access the memory independently, write-through seems to be the way to
go.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>