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Path: ...!news.nobody.at!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.arch Subject: Re: My 66000 and High word facility Date: Sun, 11 Aug 2024 14:33:33 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 28 Message-ID: <2024Aug11.163333@mips.complang.tuwien.ac.at> References: <v98asi$rulo$1@dont-email.me> <38055f09c5d32ab77b9e3f1c7b979fb4@www.novabbs.org> <v991kh$vu8g$1@dont-email.me> Injection-Date: Sun, 11 Aug 2024 16:43:27 +0200 (CEST) Injection-Info: dont-email.me; posting-host="b250ad582970d66a662cc6fd2e2f7eca"; logging-data="2894367"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19pvevxqoCSW4klrxRScfKo" Cancel-Lock: sha1:2daasvqAV9vJsjOcFnrvC73lyNY= X-newsreader: xrn 10.11 Bytes: 1919 Brett <ggtgp@yahoo.com> writes: >The lack of CPU’s with 64 registers is what makes for a market, that 4% >that could benefit have no options to pick from. They had: SPARC: Ok, only 32 GPRs available at a time, but more in hardware through the Window mechanism. AMD29K: IIRC a 128-register stack and 64 additional registers IA-64: 128 GPRs and 128 FPRs with register stack and rotating register files to make good use of them. The additional registers obviously did not give these architectures a decisive advantage. When ARM designed A64, when the RISC-V people designed RISC-V, and when Intel designed APX, each of them had the opportinity to go for 64 GPRs, but they decided not to. Apparently the benefits do not outweigh the disadvantages. Where is your 4% number coming from? - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>