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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: Instruction Tracing
Date: Mon, 12 Aug 2024 11:10:45 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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Terje Mathisen <terje.mathisen@tmsw.no> writes:
>Lawrence D'Oliveiro wrote:
>> On Sun, 11 Aug 2024 14:44:38 GMT, Anton Ertl wrote:
>>=20
>>> Power (IIRC) and Alpha don't have delayed branches.
>>=20
>> Not only does POWER not have delayed branches, but I recall the IBM fol=
>ks
>> claiming in the initial publicity that branches could often execute in
>> zero clock cycles--that is, fully overlapped with surrounding
>> instructions.
>
>Afair, the original POWER had 3 chips, with branches in a separate unit=20
>from integer/logic ops, right?

Looking at <https://en.wikipedia.org/wiki/POWER1>, the RIOS-1
configuration has 9 chips: ICU, FPU, FXU (integer unit), SCU (storage
control), 4xDCU (data cache), I/O Unit.  The RIOS-9 configuration has
only 2 DCUs (7 chips total).

>It also had multiple (8?) sets of compare result flags in order to avoid =
>making them a speed limiter.

I wonder how much that is used.  There is only one carry bit.

>Yeah, the R part was intended to make latency a single cycle for _most_=20
>instructions.

It was mainly meant to increase the *throughput* to one instruction
per cycle; that includes instructions like loads that have a
latency > 1 cycle.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>