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Path: ...!weretis.net!feeder8.news.weretis.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.arch Subject: Re: Decrement And Branch Date: Tue, 13 Aug 2024 13:28:07 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 31 Message-ID: <2024Aug13.152807@mips.complang.tuwien.ac.at> References: <v9f7b9$3qj3c$1@dont-email.me> Injection-Date: Tue, 13 Aug 2024 15:53:05 +0200 (CEST) Injection-Info: dont-email.me; posting-host="13d17528895f3c8615cb3d6aef8bb091"; logging-data="4107155"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18wX3tIRflv3JOX8sphBWDQ" Cancel-Lock: sha1:OGxGJQ1jRhGBe35t/l90/1qjLYk= X-newsreader: xrn 10.11 Bytes: 2372 Lawrence D'Oliveiro <ldo@nz.invalid> writes: >The original designers of POWER clearly thought there was a point to >having such instructions; do you agree? Sure. The question is what it was. Maybe they wanted to look good on some kernels. In the same vein they also added loads and stores with update (i.e., autoincrement/decrement addressing), and in one version of the architecture reference manual I found the warning that these may be as slow as a separate load and update. AMD64 has LOOP. I looked at it here several times. Theoretically one can branch-predict it perfectly, but when I measured that <2016Jun16.103617@mips.complang.tuwien.ac.at> <2017Mar14.183125@mips.complang.tuwien.ac.at>, I found that they just use history-based branch prediction for these instructions like everybody else. I think that the major reason is that in an OoO CPU the OoO part would need to move the count to the front end, and either let the front end wait until that is done, or introduce some mechanism to let the front end run ahead and, when the count finally becomes available to the front end, update it to the right value where the front end is now. Moreover, at least some AMD64 CPUs take more cycles for a LOOP than for the equivalent "sub; jne" sequence <2017Mar15.141411@mips.complang.tuwien.ac.at> - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>