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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: Decrement And Branch
Date: Wed, 14 Aug 2024 09:10:01 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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Lawrence D'Oliveiro <ldo@nz.invalid> writes:
>Like I said, I wondered why this sort of thing wasn't more common ...

For the early RISCs, the pipeline was designed for early branch
execution.  Performing an ALU op before the branch did not fit that
kind of pipeline.

However, having a branch-and-subtract would have been possible.  But
how would that have interacted with the branch delay slots that many
of them had?  I guess one could perform the subtract before the
instruction in the delay slot, and take the branch afterwards (if it
is taken). 

So it would actually fit.  Why was it not done?  Maybe the idea was
that induction-variable elimination would usually eliminate the
subtract anyway, so why complicate the architecture with such an
instruction?

For over a decade, Intel decoders have decoded many sequences of ALU
and branch instructions into one uop, so they can do at a
microarchitectural level what you are asking about at the architecture
level.  Other microarchitectures have followed this pattern, and
RISC-V seems to make a philosophy out of this.

ARM A64 OTOH seems to put everything into an instruction that fits in
32 bits, and while they have instructions (TBNZ and TBZ) that tests a
specific bit in a register and branch if the bit is set or clear, they
have not added a subtract-and-branch or branch-and-subtract
instruction.  Apparently the uses for such an instruction are not that
frequent.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>