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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: number of registers
Date: Wed, 21 Aug 2024 15:28:05 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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Message-ID: <2024Aug21.172805@mips.complang.tuwien.ac.at>
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Michael S <already5chosen@yahoo.com> writes:
>On Wed, 21 Aug 2024 12:00:47 GMT
>anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:
>
>> 
>> On the Intel side, LD-OP-ST is split into three uops according to
>> everything I have read.  Apparently they are satisfied with this
>> approach, or they would have gone for something else.
>> 
>> - anton
>
>AFAIK, on the Intel side, LD-OP-ST is decoded into 4 uOps that are
>immediately fused into 2 fused uOps.

Which 4 uops and 2 macroops are those?  My guess is that ST is
store-data and store-address uops, and ld and op are one uop each.

>They travel through rename phase
>as 2 uOps.

Interesting.  But yes, only two values are generated for physical
registers: the result of the load and the result of the op.  So I
expect that the two store parts are tacked onto the op on the way
through the renamer, and then that macroop is split into its parts on
the way to the schedulers.

>I am not sure if they are split back into 4 uOps before or
>after OoO schedulers, but would guess the former.

Golden Cove is depicted as having an op scheduler, a load scheduler
and a store scheduler, so they have to split the ld-op-store into at
least three parts for scheduling.

Sunny Cove is depicted as having an op scheduler, a store data
scheduler, and two AGU schedulers, which would again mean at least
three parts, but this time with a different split.

Both based on
<https://chipsandcheese.com/2021/12/02/popping-the-hood-on-golden-cove/>

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>