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Article <2024Aug21.184537@mips.complang.tuwien.ac.at>
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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: number of registers
Date: Wed, 21 Aug 2024 16:45:37 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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Message-ID: <2024Aug21.184537@mips.complang.tuwien.ac.at>
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Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:
>There are also some savings in reduced I-cache usage (possibly leading 
>to higher I-cache hit rate), reduced memory I-fetch memory bandwidth 
>required, etc, though these may be modest at best.

Let's see how that works out.  I am using the code size numbers
from <2024Jan4.101941@mips.complang.tuwien.ac.at>:

   bash     grep      gzip
  595204   107636    46744 armhf    16 regs load/store     32-bit
  599832   101102    46898 riscv64  32 regs load/store     64-bit
  796501   144926    57729 amd64    16 regs ld-op ld-op-st 64-bit
  829776   134784    56868 arm64    32 regs load/store     64-bit
  853892   152068    61124 i386      8 regs ld-op ld-op-st 32-bit
  891128   158544    68500 armel    16 regs load/store     32-bit
  892688   168816    64664 s390x    16 regs ld-op ld-op-st 64-bit
 1020720   170736    71088 mips64el 32 regs load/store     64-bit
 1168104   194900    83332 ppc64el  32 regs load/store     64-bit

So the least code size is from a load/store architecture with 16
registers, followed (or preceded in the case of grep) by a load/store
architecture with 32 registers.  The instruction sets that have
loap-op and load-op-st instructions result in bigger code.  The
different sizes of armhf (ARMv7) and armel (ARMv4t-ARMv6t) show that
there is more to code sizes than just the architecture.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>