Path: ...!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail
From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: Keeping other stuff with addresses (was: What is an N-bit machine?)
Date: Sun, 01 Dec 2024 09:28:26 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
Lines: 25
Message-ID: <2024Dec1.102826@mips.complang.tuwien.ac.at>
References: <memo.20241128153105.12904U@jgd.cix.co.uk> <20241128185548.000031c9@yahoo.com> <vidtpt$pon$1@gal.iecc.com> <2024Nov30.072829@mips.complang.tuwien.ac.at> <2024Nov30.123536@mips.complang.tuwien.ac.at> <vieuks$1n5ve$1@dont-email.me> <2024Nov30.175756@mips.complang.tuwien.ac.at> <20241130193206.00005c49@yahoo.com> <2024Nov30.190858@mips.complang.tuwien.ac.at> <20241130202851.00005eca@yahoo.com>
Injection-Date: Sun, 01 Dec 2024 10:38:11 +0100 (CET)
Injection-Info: dont-email.me; posting-host="2f8875923af00366d4283fd291a6efc2";
	logging-data="2500983"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX18bHFNJHfhzTbs8CshmZjHP"
Cancel-Lock: sha1:D1NTMQGWRHaP1hCzuIHv08Ot0dc=
X-newsreader: xrn 10.11
Bytes: 2299

Michael S <already5chosen@yahoo.com> writes:
>On Sat, 30 Nov 2024 18:08:58 GMT
>anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:
>> The widest arithmetic registers on AMD64 with AVX-512 are the ZMM
>> registers with 512 bits each.  Sure, they are used for arithmetic on a
>> sequence of individually narrower data, but the registers have 512
>> bits nonetheless.
....
>8x64 is not the same as 512.

Alternative facts?  Anyway, the ZMM registers are used for arithmentic
and are 512 bits wide; this just shows that "size of arithmetic
registers" does not reflect what we usually mean with "N-bit", and
John Levine has refined his criterion accordingly.

>You don't call 2-way superscalar 64-bit CPU 128-bit.

The "size of arithmetic registers" criterion would call the 21064 a
64-bit CPU.  It's not my criterion, but it happens to agree with my
criterion for this CPU.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>