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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Intel Generations (was: Faster div or 1/sqrt approximations (was: Continuations)
Date: Sun, 21 Jul 2024 12:27:15 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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Michael S <already5chosen@yahoo.com> writes:
>Gen 2 is Sandy Bridg
>Gen 3 is Ivy Bridge which is very similar core microarchitecture
>Gen 4 is Haswell
>Gen 5 is Broadwell which is similar, but has few changes 
>Gen 6,7,8,9 and majority of 10 is all the same microarchitecture -
>Skylake.
>11 is mostly Tiger lake and partially Ice Lake and Rocket Lake. All
>three are different from each other on silicon proces side, but ver
>similar on core microarcheticture.
>12 is Alder Lake that has P cores and E cores. Microarchitecture of P
>core is called Golden Cove.

Introduction year = Generation + 2009

That's what's important to Intel's marketing, and it explains why
there are different microarchitectures with the same generation, and
the same microarchitecture with different generations.

However, they gave Rocket Lake (introduce 2021) 11th-Generation
numbers, probably in anticipation of the introduction of Alder Lake
later that year.

AFAIK all Ice Lakes are "10th generation".  I also used to think that
the microarchitectural difference between Ice Lake, Tiger Lake, and
Rocket Lake are very minor, but it turns out that they are
significant.  I remember (IIRC the source was chipsncheese) one
difference being that Rocket Lake can optimize dependent moves, but
Tiger Lake cannot (apparently a bug that was fixed properly in Rocket
Lake, but only by turning off that feature in Tiger Lake and Ice
Lake).  I also saw differences in measurements I made:

http://www.complang.tuwien.ac.at/anton/tmp/intel-p-evo-eps-converted-to.pdf

The different lines are for different benchmarks, and the y axis
represents a speedup, of Gforth with the cib optimization over Gforth
without it.  If Rocket Lake and Tiger Lake had the same
microarchitecture, I would expect flat lines between them (I don't
think that these benchmarks are much influenced by the Tiger Lake's
larger L2 cache), but we see quite a bit of difference for many
benchmarks.

Other views at the same data are:

http://www.complang.tuwien.ac.at/anton/tmp/opt-ipc-uarch.eps
http://www.complang.tuwien.ac.at/anton/tmp/unopt-ipc-uarch.eps

These are IPC results for the same benchmarks, with the results sorted
for each microarchitecture.  opt is with the cib optimization, unopt
without.  Tigerlake is the second-lightest blue and Rocket Lake the
third-lightest blue, and they are close to the top in both graphs.
But you can see that they have different IPC numbers for a number of
benchmarks.  It's better visible in the opt graph,

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>