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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: Chipsandcheese article on the CDC6600
Date: Mon, 22 Jul 2024 16:33:28 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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scott@slp53.sl.home (Scott Lurndal) writes:
>anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>>However, the main reason why reservation stations won is because
>>hardware branch prediction outpaced compiler branch prediction since
>>the early 1990s*, and because the reorder buffer was invented, neither
>>of which is due to anything done in any S/360 model or the CDC 6600).
>
>FWIW, The burroughs medium systems had hardware branch
>prediction circa 1979.  It had some warts, however,
>when used in SMP configurations.
>
>Basically, the hardware would modify the branch opcode in
>memory after every branch to track the last two taken/not-taken
>states.

That sounds like the two-bit scheme that early conditional branch
predictors used, but inlined in the instructions and thus
architecturally visible (whereas branch prediction is normally
microarchitecture, i.e., architecturally invisible).  These two-bit
schemes were about as good as the better compiler-based schemes (IIRC
10% mispredictions on typical integer code).  It was branch prediction
schemes with global history tables etc. that made hardware branch
prediction much more accurate and meant that OoO execution
outperformed EPIC.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>