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Path: ...!weretis.net!feeder8.news.weretis.net!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.arch Subject: Re: Chipsandcheese article on the CDC6600 Date: Mon, 22 Jul 2024 16:40:48 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 42 Message-ID: <2024Jul22.184048@mips.complang.tuwien.ac.at> References: <v7fss8$3f712$1@dont-email.me> <v7fuqu$3fg81$2@dont-email.me> <2k3q9j1lqngjsfmts49q6l3825nipf91rq@4ax.com> <v7k0gm$8pms$13@dont-email.me> <a11cff7fe912529a0a7962163afe43d8@www.novabbs.org> <v7k7ok$a7tn$5@dont-email.me> <lg6gtgFlcf1U1@mid.individual.net> <20240722130827.00004fea@yahoo.com> <2024Jul22.145235@mips.complang.tuwien.ac.at> <defdaa4bb6c9c6f07513c29c9d82af18@www.novabbs.org> Injection-Date: Mon, 22 Jul 2024 18:51:25 +0200 (CEST) Injection-Info: dont-email.me; posting-host="6d4d8ad3d9aaace8f70489062bf437eb"; logging-data="773181"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/SI2gtUoKV6RL0Klwq2BAY" Cancel-Lock: sha1:rI9/yuXNnNZ+Uwmu4LLGUt/EnnA= X-newsreader: xrn 10.11 Bytes: 3216 mitchalsup@aol.com (MitchAlsup1) writes: >> If hardware branch prediction had never been invented or had turned >> out to be a dud, maybe we would all be using EPIC architectures that >> use scoreboards rather then reservation stations; or maybe the > >CDC 7600 predicted backwards branches to be taken That's a primitive form of compiler branch prediction. More advanced schemes had a direction hint in the instruction. These schemes are not hardware branch prediction as far as "compiler vs. hardware branch prediction" is concerned. >> register interlocks that were used in advanced in-order RISCs (those >> that Mitch Alsup calls OoO) and AFAIK in IA-64 implementations were >> good enough and one would have done without scoreboard. > >Register interlocks is the means to allow GHW to move instructions >around in the pipeline--you just have to obey RAW, WAR, and WAW >hazards. What is GHW? Stanford MIPS and most of MIPS R2000/R3000 moved instructions in the pipeline without interlocks. It's in their name: Microprocessor without interlocked pipeline stages. >> [*] More supercomputing-oriented people may claim that it has to do >> with the number of in-flight memory accesses, but actually IA-64 shone >> on SPEC FP (where in-flight memory accesses are more important than >> for SPECint), so it seems that there are ways to get the needed >> in-flight memory accesses with in-order execution. > >IA-64 had 2× the number of pins compared to its x86 brethren. >No wonder it could consume more BW. Did not help it a bit with integer code. If the myth was true that only OoO enables many in-flight memory accesses, it would not help for bandwidth-hungry code, either. The fact that IA-64 implementations could make use of the bandwidth busts that myth. - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>