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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: IPC (was: Reservation stations)
Date: Mon, 22 Jul 2024 17:39:10 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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EricP <ThatWouldBeTelling@thevillage.com> writes:
>MitchAlsup1 wrote:
[...]
>(Nobody bats an eye at using kilobytes for the branch predictor.)

IIRC it's in the hundreds of KB on the larger cores.  But it pays
off.

>> One should also note that these machines deliver 1-2 I/c RMS
>> regardless of their Fetch-Decode-FU widths.
>
>Yes, its mostly all for naught.

Evidence?  If it was all for naught, people would not build these big
cores.

Counterevidence:

http://www.complang.tuwien.ac.at/anton/tmp/opt-ipc-uarch.eps

Goldencove has a median IPC of almost 4 for these benchmarks (a bunch
of Forth benchmarks running on Gforth).  You also see a steady advance
between generations, from Sandybridge to Goldencove, from Silvermont
to Gracemont, from K8 to Zen3, and also the expected differences
between A72, A76, and Firestorm.  And the in-order cores are the
dashed ones at the bottom.  Particularly remarkable is Gracemont,
which usually has better IPC than Skylake and comparable IPC to
Firestorm.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>