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Path: ...!news.nobody.at!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: anton@mips.complang.tuwien.ac.at (Anton Ertl) Newsgroups: comp.arch Subject: Re: Arguments for a sane ISA 6-years later Date: Fri, 26 Jul 2024 17:00:07 GMT Organization: Institut fuer Computersprachen, Technische Universitaet Wien Lines: 47 Message-ID: <2024Jul26.190007@mips.complang.tuwien.ac.at> References: <b5d4a172469485e9799de44f5f120c73@www.novabbs.org> <v7ubd4$2e8dr$1@dont-email.me> <v7uc71$2ec3f$1@dont-email.me> Injection-Date: Fri, 26 Jul 2024 19:17:33 +0200 (CEST) Injection-Info: dont-email.me; posting-host="db2ff68befcdcab7a74f905c9b0b3b66"; logging-data="3066015"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ubb9uRQpZR2hfULRTXu6Y" Cancel-Lock: sha1:F4M0rytBOgd3y8rIn0H8XzfDlxU= X-newsreader: xrn 10.11 Bytes: 2986 "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> writes: >On 7/25/2024 1:09 PM, BGB wrote: >> At least with a weak model, software knows that if it doesn't go through >> the rituals, the memory will be stale. There is no guarantee of staleness, only a lack of stronger ordering guarantees. >The weak model is ideal for me. I know how to program for it And the fact that this model is so hard to use that few others know how to program for it make it ideal for you. >and it's more efficient That depends on the hardware. Yes, the Alpha 21164 with its imprecise exceptions was "more efficient" than other hardware for a while, then the Pentium Pro came along and gave us precise exceptions and more efficiency. And eventually the Alpha people learned the trick, too, and 21264 provided precise exceptions (although they did not admit this) and more efficieny. Similarly, I expect that hardware that is designed for good TSO or sequential consistency performance will run faster on code written for this model than code written for weakly consistent hardware will run on that hardware. That's because software written for weakly consistent hardware often has to insert barriers or atomic operations just in case, and these operations are slow on hardware optimized for weak consistency. By contrast, one can design hardware for strong ordering such that the slowness occurs only in those cases when actual (not potential) communication between the cores happens, i.e., much less frequently. >and sometimes use cases do not care if they encounter "stale" data. Great. Unless these "sometimes" cases are more often than the cases where you perform some atomic operation or barrier because of potential, but not actual communication between cores, the weak model is still slower than a well-implemented strong model. - anton -- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>