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From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: return for loop-back edges (Re: Concertlina II: Full Circle)
Date: Wed, 19 Jun 2024 07:58:08 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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mitchalsup@aol.com (MitchAlsup1) writes:
[the instruction that ends the loop]
>No, it is not a memref--it is a return ! using the register from the 
>VEC  instruction. You "return" to the top of the loop. There is no 
>reason to use IP+Disp, and the fact there is no register nor disp-
>lacement in LOOP enables it all to fit. In addition, when VEC executes,
>
>IP is pointing at the top of the loop, requiring no calculation 
>whatsoever.

On a related note, about a year ago I have started research on the
performance effect of (programming language) virtual-machine IP
updates in interpreters.  The dependence chains of these IP updates
create a lower bound for the execution time of the program, and it
turns out that, if the interpreter is otherwise efficient enough, this
lower bound determines performance, and that we see speedups by up to
a factor of 3 (depending on benchmark and microarchitecture) by
optimizing these IP updates.

One of the optimizations we tried out was to break the dependence
chain be saving the IP on loop entry, and using that IP when starting
the next iteration; this eliminates the IP updates of one iteration
from the dependence chain of the next iteration.

- anton
-- 
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>